The present invention relates to semiconductor devices, and more particularly to a ground-plane device which includes a field effect transistor (FET) that is formed on a silicon-on-insulator (SOI) wafer. Additionally, the present invention provides a method of fabricating a ground-plane device in which the short channel effects typically present in such devices have been substantially eliminated.
In semiconductor processing, SOI technology is becoming increasingly more important since it permits the formation of high-speed integrated circuits. In SOI technology, a relatively thin layer of semiconducting material, e.g., Si, overlays a layer of insulating material, e.g., a buried oxide region. This relatively thin layer of semiconducting material is generally the area wherein active devices such as field effect transistors (FETs) are formed in the SOI wafer. Devices formed on SOI offer many advantages over their bulk Si counterparts including higher performance, absence of latch-up, higher packing density and lower voltage applications.
Despite the advantages obtained using SOI technology, SOI technology suffers from short channel effects which are also present in bulk Si technology. As is known to those skilled in the art short channel effects tend to degrade the electronic integrity of the device and lead to unacceptable device leakage current known in the art as xe2x80x98off-currentxe2x80x99. Short channel effects are more pronounced in very large scale integration (VSLI) devices wherein the channel length is less than 1 xcexcm.
In view of the short channel effect problem mentioned above with SOI devices, there is a continued need for developing a new and improved SOI device which substantially eliminates the short channel effects.
One object of the present invention is to provide a ground-plane device that has a topography that is not planar.
Another object of the present invention is to provide a ground-plane device in which the advantages of both ground-plane devices and SOI devices are achieved in a single device.
A further object of the present invention is to provide a ground-plane SOI device in which the deep source/drain perimeter junction capacitance is substantially eliminated, and the area component of the junction capacitance is reduced compared to conventional ground-plane devices.
These and other objects and advantages are achieved in the present invention by providing a ground-plane SOI device in which the buried oxide layer of the device has been modified, i.e., etched, to have a topography that is not planar. The buried oxide layer of the present invention is distinct from a conventional buried oxide layer in that it is not planar and does have a specific thickness like a conventional buried oxide layer. Moreover, the non-planar buried oxide layer of the present invention layer has a thickness that is smaller under the gate region as compared to the combined thickness of corresponding oxide layers that are formed on a recessed surface of a Si substrate of a SOI wafer in regions below the source/drain regions.
In one aspect of the present invention, a method of forming a ground-plane SOI device having a non-planar buried oxide layer is provided. Specifically, the method of the present invention comprises the steps of:
(a) implanting a ground-plane doping region into a top portion of a Si substrate of a silicon-on-insulator (SOI) wafer, said SOI wafer having a buried oxide layer formed on said Si substrate and a top Si-containing layer formed on said buried oxide layer;
(b) forming a gate region on a portion of said top Si-containing layer of said SOI wafer, said gate region including a gate dielectric formed on said top Si-containing layer, a gate conductor formed on said gate oxide and a hard mask formed on said gate conductor;
(c) forming halo implant and source/drain extension regions in said top Si-containing layer of said SOI wafer;
(d) forming first spacers on said gate dielectric so as to protect vertical sidewalls of said gate conductor and said hard mask;
(e) removing portions of said top Si-containing layer of said SOI wafer so as to expose portions of said buried oxide layer;
(f) etching said exposed buried oxide layer so as to form a non-planar buried oxide layer;
(g) forming second spacers on said non-planar buried oxide layer so as to protect said first spacers and exposed vertical sidewalls of said top Si-containing layer;
(h) removing exposed portions of said non-planar buried oxide layer so as to expose underlying portions of said Si substrate of said SOI wafer;
(i) recessing exposed portions of said Si substrate and providing a lateral undercut region in said Si substrate beneath said gate region;
(j) forming an oxide liner on all exposed surfaces of said Si substrate and filling said recess and said undercut region with an oxide fill material, said oxide fill material and said oxide liner having a combined thickness that is greater than the thickness of the non-planar buried oxide layer under said gate region; and
(k) removing said second spacers and forming doped polysilicon spacers in areas previously occupied by said second spacers.
After conducting steps (a)-(k) above, conventional complementary metal oxide processing steps may be carried out in providing the final grounded plane SOI device. In a preferred embodiment of the present invention, the following processing steps follow steps (a)-(k) above:
(l) forming an epi polysilicon layer on said oxide fill material provided in step (j); and
(m) removing said hard mask from said gate conductor and siliciding said gate conductor and said epi polysilicon layer.
The present invention also provides a ground-plane SOI device which comprises at least a gate region that is formed on a top Si-containing layer of a SOI wafer, said top Si-containing layer being formed on a non-planar buried oxide layer, wherein said non-planar buried oxide layer has a thickness beneath the gate region that is thinner than corresponding oxide layers that are formed in regions not beneath said gate region.